Memory in integrated circuits must be tested to ensure reliability. Typically, integrated circuits are extensively tested both during and after production and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as DRAMs, are tested during production at the wafer level and after packaging. They are also routinely tested each time a computer system using the DRAMs executes a power-up routine when power is initially applied to the computer system. DRAMs are generally tested by writing known data to each location in the memory and then reading data from each memory location to determine if the read data matches the written data. As the capacity of DRAMs and other memory devices continues to increase, the time required to write and then read data from all memory locations continues to increase, even though memory access times continue to decrease.
FIG. 1 shows a block diagram of a conventional semiconductor memory device 100 having an array 140 of eight memory blocks 145. The memory array 140 includes row decoder and access circuits 125 and column decoder and access circuits 135. The memory device 100 also includes peripheral circuit 440 which includes, for example, the mode register of the memory device. Peripheral circuit 440 controls how the memory array 140, and correspondingly, the memory blocks 145, are accessed (e.g., burst type, burst length, read/write delays). Although not shown, peripheral circuit 440 is coupled to each row decoder and access circuitry 125 and column decoder and access circuitry 135. It is known that the number of memory blocks 145 that comprise memory array 140 may vary depending on the implementation. Test controller 450 is coupled to the memory device 100 through line 451. Test controller 450 provides signal information to memory device 100, peripheral circuit 440, and decoder and access circuits 135, 125 to perform testing on memory device 100. For example, test controller 450 will provide location signal information, read/write signal information, and other signal information used to implement testing operations on memory device 100.
FIG. 2 shows the configuration of the memory device 100 of FIG. 1 in greater detail. As shown, memory device 100 includes a memory array 140 having eight memory blocks 145 (FIG. 1), although only one memory block 145 is shown in FIG. 2. Memory block 145 is composed of two memory sub-blocks 155. Although described with one memory array 140, eight memory blocks 145, and two sub-blocks 155, the number of memory arrays 140, memory blocks 145, and memory sub-blocks 155 in device 100 can vary depending on the implementation. Each memory block 145 includes bit lines that extend through the sub-blocks 155. Bit lines 112, 114 are representative of the many bitlines in block 145.
Memory block 145 has 1024 rows, M columns, and two sub-blocks 155, where each sub-block 155 has 512 rows. Conventionally, each row of memory block 145 is numbered sequentially starting with row number 0 as the first row in the memory block 145 and row number 1023 being the last row in the memory block 145. Row number 511 is the last row in the upper sub-block 155 and row number 512 is the first row in the lower sub-block 155. Although described with reference to memory block having 1024 rows of memory, the number of rows of memory may vary depending on the implementation.
FIG. 3 shows a memory sub-block 155 of FIG. 2 in greater detail. Memory sub-block 155 has a plurality of memory cells 170, for example, DRAM cells, that are arranged in rows 120 and columns 130, e.g., as an x-y grid. Conductive bit lines 112, 114, 116, 118 extend the length of the memory array 140 and connect bit line contacts of respective memory cells 170 within the columns. Word lines 102, 104, 106, 107, 108, 109, 110 extend the width of memory sub-block 155 and connect control terminals of the access transistors in the memory cells of their respective rows. Known peripheral column and row decoder and access circuitry 135, 125 (FIG. 1) determine, in accordance with supplied address data, selected bit lines and word lines upon which to propagate data and enable signals respectively. Although not shown in FIG. 3, each word line 102, 104, 106, 107, 108, 109, 110 is coupled to the row decoder and access circuitry 125, and each bit line 112, 114, 116, 118 is coupled to the column decoder and access circuitry 135. The location of memory cells can vary depending on the implementation. For example, although FIG. 2 shows memory cells located at some, but not all, of the intersections of row and column lines of the memory sub-block, other implementations may have memory cells at every intersection.
As indicated above, memory block 145 has 1024 rows of memory, M columns, and two sub-blocks 155, where each sub-block 155 has 512 rows of memory. Dummy rows, e.g., rows 102, 110, are not counted as part of the rows of memory. If memory sub-block 155 is the first of the two memory sub-blocks 155 (FIG. 2), then word line 104 represents the row line adjacent to the top periphery of the memory sub-block 155 and the top of the memory block 145, i.e., row number 0. Word lines 107, 109 represent the row lines adjacent to the twist 160 of the memory sub-block 155, e.g., row numbers 254, 255, 256, and 257. Word line 108 represents the row line adjacent to the bottom periphery of the memory sub-block 155, i.e., row number 510, 511.
If memory sub-block 155 is the second of the two memory sub-blocks 155 (FIG. 2), then word line 104 represents the row line adjacent to the top periphery of the memory sub-block 155, i.e., row number 512, 513. Word lines 107, 109 represent the row lines adjacent to the twist 160 of the memory sub-block 155, e.g., row numbers 766, 767, 768, and 769. Word line 108 represents the row line adjacent to the bottom periphery of the memory sub-block 155 and the bottom of the memory block 145, i.e., row number 1023.
Bit line 114 represents the column line adjacent to the left periphery of the memory sub-block 155, i.e., column 0, 1. Bit line 118 represents the column line adjacent to the right periphery of the memory sub-block 155, i.e., column M-1, M-2 if there are M columns in the memory sub-block 155. The bit lines extend through the memory block 145, therefore passing through each sub-block 155 in memory block 145 although not shown.
One known method of testing a memory device requires what is known as a brute force approach of testing the entire memory array 140. During such testing, zeroes are written to all the memory cells 170 in the memory array 140. This is followed by reading each memory cell 170 to ensure that the zeroes were correctly written and stored. Then ones are written in all the memory cells 170, which are then read to ensure that the ones were correctly written and stored.
Another known memory test is the checkerboard test, where the memory cells 170 of an array 140 are divided into two groups. The first group of memory cells 170 form the checkerboard, the second group of memory cells 170 is formed from the remaining cells also forms a similar checkerboard. In the first step of the test, ones are written to all the memory cells 170 of the first group and zeroes are written to all the memory cells 170 of the second group. In the second step, all of the memory cells 170 are read to verify that the values were correctly written to and stored by the memory cells 170. In the third step of the test, zeroes are written to all the memory cells 170 of the first group and ones are written to all the memory cells 170 of the second group. In the fourth step, all of the memory cells 170 are read to verify that the values were correctly written to and stored by the memory cells 170. The above described checkerboard approach also serves to test the memory cell-to-memory cell isolation between memory cells 170 of an array 140.
Two significant values in the testing process are Vcc and tWR. Vcc is the supply, or rail, voltage used for writing to (and refreshing) a memory cell 170. Typical testing circuitry uses a standard Vcc (e.g., 2.5V) as the full logic level, i.e., a “one.” Typical performance requirements of a semiconductor memory may be seen, for example, in the Micron datasheet 256 mb DRAM specifications at (http://download.micron.com/pdf/datasheets/dram/256MSDRAM_E.pdf).
tWR stands for Write (data) Recovery time. As is known, burst length is the word size of data that is written at a time. Burst length may be, for example, one, two, or four. Generally, tWR is referred to as the time necessary to store data into a memory cell 170 before a pre-charge can occur. If burst length is programmed to be greater than one, then tWR is the time necessary to store the last piece of data into a memory cell 170 before a pre-charge can occur. tWR is the necessary time/minimum time to guarantee that data in the write buffer can be fully written into the memory cell 170. If tWR is not satisfied, e.g., if tWR is not sufficiently long enough to store data in a memory cell 170, then the full data is not stored and a read failure, e.g., an inaccurate read, can result. Testing circuitry generally uses a standard tWR substantially similar to the tWR used in the actual performance of the memory. For example, according to the datasheet specification for the Micron 256 mb DRAM, tWR is 12 ns.
As the size of memory arrays (e.g., 140) increases, so does the time required to test the arrays. Various proposals have been made to decrease the time required to test memory arrays 140. The time required to write known data to memory array 140 has been reduced by such approaches as simultaneously writing the same data to each column of each array one row at a time. However, some types of testing require that the word lines be kept at a fixed positive voltage for an extended period of time, such as tens of milliseconds. When there are thousands of word lines in one memory device, the memory testing takes long periods of time since only one word line in each block of the memory array 140 may be accessed at a time.
An additional problem in memory testing arises because there are memory cells 170 in certain regions of a memory block 145 that are more susceptible to faults or errors. As seen in FIG. 3 memory block 145 has an area of memory cells 170 adjacent to the periphery of the memory sub-block 155 that form a fringe area. An area is adjacent if it is next to or nearby another area. The fringe area may include the first row e.g., rows 104, 108, adjacent to the dummy rows, e.g., rows 102. Further the fringe area may include the first column, e.g., columns 114, 118, adjacent to dummy columns, e.g., columns 112. A memory sub-block 155 having a folded digitline 160 (FIG. 3), e.g., a twist, has another area of memory cells 170 adjacent to the twist 160 that forms another fringe area. For example, the fringe area adjacent to twist 160 may include the rows, e.g., rows 107, 109, that are adjacent to the dummy rows, e.g., rows 110, that are located adjacent to the twist 160. A memory cell 170 in a fringe geographic region has inherent influences that can affect the reliability of the memory cell.
An edge in a memory cell implies those memory cells located adjacent to or nearby the physical boundaries of a subarray/a block/a bank. In other words, an edge includes memory cells that either are adjacent to the dummy memory cells or have strongest interference with the dummy memory cells. Edge memory cells can be affected by the physics and/or electronics of the corresponding dummy cells. Edge memory rows are rows located adjacent to or nearby the physical boundary of a subarray/a block/a bank. Edge memory rows are not necessarily limited to the closest row to the physical boundary and may include several rows close to the physical boundary. Similarly, edge memory columns are rows located adjacent to or nearby the physical boundary of a subarray/a block/a bank. Edge memory columns are not necessarily limited to the closest column to the physical boundary and may include several columns close to the physical boundary. Edge subarrays, or edge blocks, are subarrays located adjacent to or nearby the physical boundary of a memory bank.
It is known to provide dummy memory cells around the periphery of a memory sub-block 155 in order to assist process uniformity during fabrication of the memory block 145. For example, in FIG. 3 memory cells 170 disposed on word lines 102 and memory cells 170 disposed on bit lines 112 are dummy memory cells. Further, in a memory sub-block 155 having a folded digitline 160, it is known to provide dummy cells around the periphery of a folded digitline 160 in order to assist process uniformity during fabrication of the memory sub-block 155. Thus, memory cells 170 disposed on bit lines 110 are also dummy cells.
Memory cells located in certain areas of a memory block 145 tend to be weaker than other memory cells. For example, memory cells located close to an edge of the memory block 145, or edge of a sub-block 155, tend to be weaker or have a smaller margin of operation (i.e., “marginal”) than memory cells not located close to an edge. Further, memory cells located close to a folded digitline of the memory block 145, or sub-block 155, tend to be weaker than memory cells not located close to twist 160.
It is also more difficult to test memory cells located in certain areas of a memory block 145. Memory cells located close to an edge of a memory block 145, or sub-block 155, are typically separated from the edge by a dummy cell. Dummy cells typically have their word line grounded to disable their associated access transistors. Additionally, dummy cells adjacent a peripheral column of the array have their bit line coupled to an intermediate voltage. Therefore, dummy cells located close to an edge of a memory block, or sub-block, are not able to receive full voltages. Consequently, a dummy cell can influence the margin of operation of an adjacent memory cell and also the testing of the adjacent memory cell. Similarly, dummy cells located adjacent to a digitline twist affects the margin and testability of memory cells adjacent to these dummy cells.
Therefore, it is desirable to have a testing method that can effectively test discrete areas of a memory array. More specifically, it is desirable to have a testing method for testing the margin of the memory cells located in the fringe areas of a memory block, such as memory cells 170 near the periphery of the memory array 140 (or memory block 145 or sub-block 155) and memory cells near folded digitlines 160.